1. Field of the Invention
The present invention relates in general to a signal multiplexing apparatus for inputting signals with recognizable frame formats and characteristics, such as DS1, DS1E and ATM cell signals generated from exchanges or other transfer equipment, and multiplexing the inputted signals into a desired format, and more particularly to a signal multiplexing apparatus using multiconnection which is capable of storing the inputted signals into memory buffers, arranging the stored signals according to the desired format, sequentially writing address data corresponding to memory locations, in which the inputted signals and overhead are stored, into address storage memory locations on the basis of the desired format and sequentially reading the address storage memory locations to multiplex the inputted signals into the desired format.
2. Description of the Prior Art
Generally, a signal multiplexing apparatus has been proposed to input signals from exchanges or other transfer equipment and multiplex the inputted signals. The signal multiplexing apparatus is adapted to sequentially multiplex low-speed signals inputted therein to covert them into high-speed signals. This is accomplished on the assumption that signals of the same speed are multiplexed in various multiplexing steps.
In the case where input signals have different characteristics (for example, the relation between DS1 and DS1E signals or the relation between those signals and a video signal) or frames of the input signals are not synchronized with a system frame synchronous signal as shown in FIG. 1 although the input signals have the same characteristic, it is hard to multiplex the input signals into a desired format. For this reason the input signals are sequentially connected and multiplexed in the order of input signal 1, input signal 2, . . . , input signal n, input signal 1, input signal 2, . . . , as shown in FIG. 2. It is also required to insert an unnecessary stuffing bit during the multiplexing operation. Also, even when input signals with the same characteristic, synchronized with the system frame synchronous signal as shown in FIG. 3, are to be processed, it is difficult to change positions of time slots in the input signals. Further, a difficulty is present in multiplexing input signals with different formats as shown in FIG. 4, such as audio and video signals, into a desired format.